Restricted Power Diagrams on the GPU. (4th June 2021)

• Record Type: Journal Article
• Authors: Basselin, J.; Alonso, L.; Ray, N.; Sokolov, D.; Lefebvre, S.; Lévy, B.
• Is Part Of: Computer graphics forum. Volume 40:Number 2(2021)
• Page Start: 1
• Page End: 12
• Publication Date: 2021-06-04
• Subjects: CCS Concepts -- Theory of computation → Computational geometry -- Computing methodologies → Parallel algorithms; Computer graphics -- Periodicals; 006.605
• DOI: 10.1111/cgf.142610
• Languages: English
• ISSNs: 0167-7055

Abstract

Abstract: We propose a method to simultaneously decompose a 3D object into power diagram cells and to integrate given functions in each of the obtained simple regions. We offer a novel, highly parallel algorithm that lends itself to an efficient GPU implementation. It is optimized for algorithms that need to compute many decompositions, for instance, centroidal Voronoi tesselation algorithms and incompressible fluid dynamics simulations. We propose an efficient solution that directly evaluates the integrals over every cell without computing the power diagram explicitly and without intersecting it with a tetrahedralization of the domain. Most computations are performed on the fly, without storing the power diagram. We manipulate a triangulation of the boundary of the domain (instead of tetrahedralizing the domain) to speed up the process. Moreover, the cells are treated independently one from another, making it possible to trivially scale up on a parallel architecture. Despite recent Voronoi diagram generation methods optimized for the GPU, computing integrals over restricted power diagrams still poses significant challenges; the restriction to a complex simulation domain is difficult and likely to be slow. It is not trivial to determine when a cell of a power diagram is completely computed, and the resulting integrals (e.g. the weighted Laplacian operator matrix) do not fit into fast (shared) GPU memory. We address all these issues and boost the performance of the state‐of‐the‐art algorithms by a factor 2 to 3 for (unrestricted) Voronoi diagrams and a ×50 speed‐up with respect to CPU implementations for restricted power diagrams. An essential ingredient to achieve this is our new scheduling strategy that allows us to treat each Voronoi/power diagram cell with optimal settings and to benefit from the fast memory.