Hot-carrier reliability and performance study of transistors with variable gate-to-drain/source overlap. (November 2022) - Devoge, P.; Aziza, H.; Lorenzini, P.; Masson, P.; Julien, F.; Marzaki, A.; Malherbe, A.; Delalleau, J.; Cabout, T.; Regnier, A.; Niel, S.
Abstract: Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions. Highlights: Flexibility on the gate-to-drain overlap length is useful for selecting the best compromise between device performance and hot-carrier reliability. The origin of the second substrate current hump is attributed to impact ionization at the drain, source, or both depending on the overlap length. The overlap distance is correlated with the device degradation rate in HCI stress, a longer overlap giving the transistor a longer lifetime.