Performance analysis and digital application of vertical L-pattern dual tunnel diode TFET. (November 2022) - Ghosh, Puja
Abstract: In this article, we propose and simulate a novel vertical L-pattern TFET with Dual Tunnel Diode (DTD) using TCAD simulator. In this device an n + (SiGe) pocket is integrated at the source side and the concept of tunneling current through two diodes is analyzed. A broader tunnel junction area is facilitated by employing tunnel junction perpendicular to the direction of the channel. The digital performance parameters of the proposed vertical DTD device such as Subthreshold Swing (SS) and ION /IOFF ratio show better result compared to the conventional DTD TFET. The architecture of the device is systematically designed in such a way that the ION /IOFF ratio gets exaggerated by optimizing the pocket thickness. The liberation of aggregated holes by the tunnel currents eliminates the impact of kink on the device characteristics. This work also examines the impact of interface traps on DC parameters as well as digital applications of complementary vertical L-patterned DTD-TFET inverter.