Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. (November 2022)

• Record Type: Journal Article
• Authors: Rajput, Anil Kumar; Pattanaik, Manisha; Kaushal, Gaurav
• Is Part Of: Microelectronics journal. Volume 129(2022)
• Publication Date: 2022-11
• Subjects: In-Memory Computing -- Compute-disturbance -- Half select issue -- Energy efficiency -- Static Random Access Memory (SRAM) -- Binary content-addressable memory (BCAM); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105569
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture is proposed to perform energy-efficient IMBC operations. The local bit-line shared pass-gate structure addresses the half select issues with a small area overhead and achieves higher array efficiency by incorporating the bit-interleave architecture. The virtual- V SS write-assist is used in SDP8T SRAM to improve the write-margin yield ( μ − 3 σ ) by 48.99%, and multi- V T H technique improves Decoupled Read-Margin (DRM) yield by 5.26% when compared to DP8T SRAM. The Dynamical Reset Word Line (DRWL) scheme is proposed to resolve the sneak current problem and make the proposed IMC architecture more resilient to compute disturbance at non-read decouple paths during IMBC operations. Further, the Reference-based Reconfigurable Sense Amplifier (RRCSA) scheme is proposed to achieve reliable (compute-failure free) sensing for IMBC on four operands simultaneously in a single cycle, normal read, and Binary Content Addressable Memory (BCAM) operations. The 4 Kb SRAM array is implemented in 65-nm CMOS technology to analyze the SDP8T-IMC architecture. The operating frequency of 1190 MHz and average-energy consumption of 18.56 fJ/bit are achieved during IMBC operation at 1V. For BCAM operations, it achieves 0.60 fJ/search/bit energy consumption in the worst case (i.e., all data mismatch) at 1V. Cumulatively, the proposed SDP8T-IMC architecture has the highest figure of merits than the recently reported IMC architecture.