A novel capacitor recombination calibration method applied to 18-bit SAR ADC. (November 2022)

• Record Type: Journal Article
• Authors: Fan, Hua; Yang, Jingxuan; Wei, Qi; Feng, Quanyuan
• Is Part Of: Microelectronics journal. Volume 129(2022)
• Publication Date: 2022-11
• Subjects: Analog-to-digital converter (ADC) -- Calibration -- Successive approximation register (SAR) -- Data converter; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105584
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a calibration method applied to Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is designed, especially applied to the capacitive array in resistive–capacitive combined SAR ADC. Conventionally, auxiliary Digital-to-Analog Converter (DAC) foreground calibration, dynamic element matching (DEM) or digital background calibration are widely used to enhance linearity of data converters. This paper proposes an off-line capacitor selection calibration method that uses an optimal sequence of unity elements for an overall improvement of Signal to Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), differential nonlinearity (DNL) and integral nonlinearity (INL). It is worth mentioning that the capacitor mismatch only needs to be calibrated after power on, this kind of foreground calibration will not increase the power consumption of ADC during the normal operation, while the background calibration will consume power consumption all the time. It is important that the calibration proposed is highly relied on a high resolution comparator. This paper provides a high resolution comparator design, the resolution of the comparator reaches 8.35 μ V, which already satisfies the demand of a 18-bit differential SAR ADC. During the process of calibration, all capacitors are divided into unit capacitors, and then the capacitors are sorted, reorganized to form each bit. The calibration method is verified by simulating a 18-bit SAR ADC with 500 Monte-Carlo runs, the simulation results show that the average value of SFDR is enhanced by about 36 dB and the average value of SNDR is enhanced by about 27 dB. Therefore, the proposed method is simple and significantly improves the static and dynamic performance of the ADC without obvious additional hardware, and greatly saves area and power consumption. Finally, it is worth mentioning that in high-precision SAR ADCs design, especially above 16 bits, comparator noise and the voltage coefficient of capacitors are the main factors limiting ADC performance, which are not considered in this work.