Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition. (November 2022)

• Record Type: Journal Article
• Authors: Pourahmad, Ali; Dehghani, Rasoul; Ahmadi-Mehr, Seyed Amir-Reza; Lotfi, Reza
• Is Part Of: Microelectronics journal. Volume 129(2022)
• Publication Date: 2022-11
• Subjects: Analog-to-digital converter (ADC) -- Successive approximation register (SAR) -- Digital-to-analog converter (DAC) -- Binary search algorithm -- Asynchronous control logic -- DAC-less SAR (DLSAR); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105585
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μ m CMOS process, the designed 8-bit DLSAR ADC consumes 150 μ W of power at 2 MS / s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS / s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç / c-s.