REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip. (November 2022)

• Record Type: Journal Article
• Authors: Ouyang, Yiming; Xu, Dongyu; Chen, Zhimou; Chen, Rongjing; Zhou, Wu; Liang, Huaguo
• Is Part Of: Microelectronics journal. Volume 129(2022)
• Publication Date: 2022-11
• Subjects: Wireless network on chip -- Power gating -- Reconfigurable -- Energy-efficient -- Wireless interface; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105600
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Currently, on-chip routers consume the majority of the power budget. Moreover, the static power consumption has taken up a significant fraction of the total power consumption in the router. Especially in the light traffic state, the router idle time is notable, but fragmented owing to the impact of some burst traffic, increasing the challenge of reducing static power consumption through power gating. In this paper, a reconfigurable and energy-efficient router architecture design (REE) is proposed: bypass connections are set for routers, and deflection rules are formulated to ensure that routers maintain connectivity in the network under power gating situation, and reduce the deflection rate of packets encountering sleeping routers. Meanwhile, a reusable predictor is introduced to efficiently predict the idle time to wake up the sleeping router appropriately. In addition, the fine-grained power gating (PG) design is introduced in the wireless interface of wireless routers (WRs) to obtain the scheme REE+, which reduces the idle time of transmitter (TX) components and effectively saves the static power consumption of Wireless Interface. Experiments demonstrate that both the REE and REE + schemes in this paper have negligible impact on latency as well as throughput, while the energy savings are significant: 64.5% and 68.3% average static power savings for REE and REE + schemes, respectively, compared to No_PG, and 13.7% and 20.5% average improvement in terms of static power saving compared to Turn-on on Turn (TooT), respectively. Highlights: In order to optimize router energy efficiency and to and avoid performance penalties due to power gating routers, this paper proposes reconfigurable and energy-efficient WiNoC routers with the following main contributions. First, we propose reconfigurable router designs with a combination of coarse and fine granularity. The Schemes make the TX side of WI and the router go to sleep when idle, guaranteeing the connectivity of the router in the network. In addition, a deflection rules are formulated to effectively avoid deflection of the router and ensure deadlock-free routing. Next, we propose a new router wake-up mechanism to reduce the number of times to wake up the router, effectively prolonging the sleep time of PG router. Finally, the evaluations illustrate that compared with the TooT scheme, both REE and REE+ schemes have negligible impact on latency and throughput, and achieve significant energy savings.