Review—Current Mirror Analysis and Design in CNTFET and CMOS Technology Including Noise Effects. (1st October 2022)

• Record Type: Journal Article
• Authors: Marani, R.; Gelao, G.; Perri, A. G.
• Is Part Of: ECS journal of solid state science and technology. Volume 11:Number 10(2022)
• Publication Date: 2022-10-01
• Subjects: Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2162-8777/ac9758
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : In this paper at first we review a procedure that, through the design of a basic current mirror, allows a comparison between CNTFET and MOS technology. For every simulation parameters of merit, such as relative error in reference current replication and small-signal output resistance, are evaluated in order to show the differences between the two considered technologies. Then the analysis is carried out considering also the effects of noise. For reference current of 1 μ A and 10 μ A the output static and dynamic characteristics are better in the case of CNTFET, but for all cases the output noise current is always higher for the CNTFET than for the MOS. The software used is Advanced Design System (ADS) which is compatible with the Verilog A programming language.