Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers. (1st October 2022)

• Record Type: Journal Article
• Authors: Van Vaerenbergh, Thomas; Hooten, Sean; Jain, Mudit; Sun, Peng; Wilmart, Quentin; Seyedi, Ashkan; Huang, Zhihong; Fiorentino, Marco; Beausoleil, Ray
• Is Part Of: JPhys photonics. Volume 4:Number 4(2022)
• Publication Date: 2022-10-01
• Subjects: wafer-level testing -- silicon photonics -- adjoint-inspired -- inverse design -- grating coupler; Photonics -- Periodicals; 621.365
• DOI: 10.1088/2515-7647/ac943c
• Languages: English
• ISSNs: 2515-7647

Abstract

Abstract: Recently, silicon photonics foundries started providing access to new dielectric stacks which can be utilized to reduce optical I/O losses. For example, in a hybrid c-Si/SiN platform, inverse design techniques can be used to create novel dual layer grating coupler (GC) designs which, in simulations, reach state-of-the-art performance. In this paper, we experimentally validate such designs for perfectly vertical single-polarization GCs in the O-band consisting of a single-etch c-Si layer with a patterned SiN overlay, fabricated using a 193 n m DUV immersion lithography process on 300 m m wafers. Here, we investigate designs generated by two different design paradigms: inverse design based on the adjoint method and adjoint-inspired design. Using wafer-level testing, we experimentally demonstrate a record low median insertion loss (IL) of 1.3 d B (with interquartile range of ∼ 0.1 – 0.2 d B ) for perfectly vertical coupling in DUV lithography compatible devices which is a ∼ 0.5 d B improvement over previously demonstrated single-layer, single-etch c-Si 0 d e g GCs.