Bias stress instability in multilayered MoTe2 field effect transistors under DC and pulse‐mode operation. Issue 4 (20th January 2021) - Seo, Seung Gi; Jeong, Jinheon; Kim, Seung Yeob; Kim, S.; Kim, Kwangtaek; Kim, Kyuwon; Jin, Sung Hun
Abstract: Here, bias stress instability on multilayered MoTe2 field effect transistors (m‐MoTe2 FETs) with encapsulation of hydrophobic polymers (cyclic transparent optical polymer) is systematically investigated under DC and pulse mode operation. During DC mode stress, the threshold voltage shift (Δ V th ) under positive bias stress is at least three times larger than that of negative stress due to high hole barrier (∼0.57 eV), compared with electron barrier (∼0.18 eV). However, Δ V th in positive pulse mode stress is significantly reduced with decrease of a duty cycle, as compared with that of negative stress. With isolation from external gas ambient effects such as H2 O and O2, shallow electron traps in multilayered MoTe2 field effect transistors are identified as one of strong candidates to cause bias polarity dependency on Δ V th in pulse mode. Moreover, recovery time for traps, involved during positive bias stress, is six times faster than that of negative stress, substantiating that shallow electron traps and their fast detrapping are one of key origins. In practice, optimisation of pulse mode operation via bipolar switching can be potentially utilised for minimisation of device instability during the operation of multilayered MoTe2 field effect transistors devices and their circuits.