Spectroscopic X-ray imaging at MHz frame rates — the HEXITECMHz ASIC. (1st October 2022)

• Record Type: Journal Article
• Authors: Jones, L.; Bell, S.; Cline, B.; Gardiner, T.; Hart, M.; Prydderch, M.; Seller, P.; Veale, M.; Wilson, M.
• Is Part Of: Journal of instrumentation. Volume 17:Number 10(2022)
• Publication Date: 2022-10-01
• Subjects: Electronic detector readout concepts (solid-state) -- Front-end electronics for detector readout; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/17/10/C10012
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: The HEXITECMHz ASIC has been developed for the HEXITECMHz Detector System, to deliver spectroscopic x-ray imaging at frame rates up to 1 MHz for future high-flux-rate applications. Optimised for sensing electron signals from detector materials such as CdTe, CdZnTe, GaAs and p-type silicon detectors, the design has an array of 80 × 80 pixels on a pitch of 250 μm, with each pixel capable of measuring single x-ray photons up to energies of 300 keV, with a resolution of 1 keV FWHM. The induced charge signals that are measured by the ASIC will typically be due to the drift of electrons in the sensor material. However, each pixel is also capable of measuring signals of the opposite polarity with magnitudes of up to 20 keV. These events are induced by weighting potential crosstalk and trapping in the sensor and can be exploited in order to provide further improvements in the spatial and spectroscopic performance of the detector. The signals from pixels are digitized every 1 μs by 12-bit time-to-digital converters. This gives a maximum of 107 photons s −1 mm −2 that can be measured. However, for spectroscopic imaging the occupancy should be limited to 10% in each frame to reduce the charge sharing events. This gives a count rate limit of 106 photons s −1 mm −2 which is two orders of magnitude greater than the previous HEXITEC ASICs. To save power, each converter is shared between groups of eight pixels. Each 76.8 kbit data frame is Aurora 64b/66b encoded and serialised over 20 lanes of differential CML, all operating in parallel at 4.1 Gbps. The ASIC can free run with an asynchronous source or can be synchronized with a pulsed source using the SYNC control input. Expected power consumption is 12–15 W from a 1.8 V supply.