Threshold voltage of p-type triple-gate junctionless transistors. (November 2022) - Oproglidis, T.A.; Tassis, D.H.; Tsormpatzoglou, A.; Karatsori, T.A.; Theodorou, C.G.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C.A.
Highlights: Threshold voltage of p-type triple-gate junctionless transistors. Correction of the drain current from the impact of series resistance. Extraction of two threshold voltages using the double derivative method in devices exhibiting weak short-channel effects. Origin of the two threshold voltages from two dimensional numerical simulations. Impact of top and side gates' interface states. Abstract: The threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is studied experimentally using the transconductance derivative (dgm /dVg ) method, after correcting the drain current from the impact of series resistance. The effect of series resistance on the dgm /dVg behavior is highlighted. In the investigated devices, the high series resistance affects the dgm /dVg behavior more than the short-channel effects. The results show that, in addition to the flat-band voltage, for the first time two threshold voltages Vth1 and Vth2 are observed within the partial depletion region in devices with channel length varying from 95 to 25 nm. Numerical simulations of the holes density distribution reveal the absence of corner effects due to the unique bulk neutral conduction, whereas Vth1 and Vth2 correspond to the threshold voltages of the side gates and top gate, respectively. The correct extraction of the flat-band voltage has been confirmed with numerical simulations of the holes density distribution. Experimental measurements of p-type JLTs with variable being the fin width indicate that the threshold voltages Vth1 and Vth2 are due to the different interface states density at the side and top gates.