On the Interpolation from Transistor Figures of Merit to Compact Model Parameters. Issue 20 (2022)

• Record Type: Journal Article
• Authors: Hahne, Lukas; Wagner, Jakob; Gonzalez, Fabio A. Velarde; Giering, Kay-Uwe; Lange, André
• Is Part Of: IFAC-PapersOnLine. Volume 55:Issue 20(2022)
• Page Start: 1
• Page End: 6
• Publication Date: 2022
• Subjects: nano -- micro-technologies -- modeling -- simulation -- analysis of reliability; Automatic control -- Periodicals; 629.805
• DOI: 10.1016/j.ifacol.2022.09.063
• Languages: English
• ISSNs: 2405-8963

Abstract

Abstract: Circuit simulations are an important step in the verification process of integrated circuits during design projects. They employ compact models that describe the behavior of integrated transistors depending on technology details, geometry, bias conditions (voltages), etc. The parametrization of these models is a complex task and requires expert knowledge. Microscopic wear-out mechanisms cause the behavior of integrated transistors to change over time. By applying over-stress conditions to test transistors, these changes in the behavior can be observed in lab experiments, and they are typically described in terms of wafer level reliability models. Aging simulations investigate the effect of shifts in the transistor behavior on the performance of an integrated circuit in its operating life. To this end, degradation models have to be established to transfer the observed changes in the transistor behavior into shifts of compact model parameters. In this paper, we present an interpolation approach to perform this task based on wafer level reliability models for the changes in the device behavior, as well as further aspects of mapping the observed behavior onto compact model parameters.