A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS. (October 2022)

• Record Type: Journal Article
• Authors: Sun, Ting; Yu, Qi; Xu, Daiguo; Li, Jing; Wu, Ke-Jun; Zhang, Zhong; Pang, Yun; Wang, Yan; Ning, Ning
• Is Part Of: Microelectronics journal. Volume 128(2022)
• Publication Date: 2022-10
• Subjects: Successive approximation registers (SAR) -- Analog-to-digital converter (ADC) -- Adaptive asynchronous logic (AAL) -- Non-binary bridge split capacitor array -- Least mean square (LMS) -- High-speed SAR logic; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105572
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A 12-bit 250-MS/s adaptive asynchronous successive approximation registers analog-to-digital converter (SAR ADC) with a Non-binary segmented split capacitor array is proposed. The Non-binary bridge split capacitor array leads to much larger units with reduced total capacitance and allows for reducing digital-to-analog converter (DAC) settling time and power consumption. The reset time of the comparator is automatically and precisely adjusted according to the settling time required by each capacitor of the non-binary capacitor array, which accelerates the ADC quantization. With the proposed adaptive asynchronous logic (AAL), the settling time utilization will reach 98.6% and the overall ADC's speed can be increased by 30%. The circuit was designed in 28 nm CMOS technology. The mismatch of the capacitor is calibrated by the Least Mean Square (LMS) background calibration for high speed and low power consumption. Based on post-layout simulations, the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.92 dB at 250 MS/s sampling rate and consumes 2.76 mW, resulting in a figure of merit of 5.43fJ/conversion-step. The ADC core occupies an active area of only 100 μm × 350 μm.