Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors. (October 2022)

• Record Type: Journal Article
• Authors: Manikandan, P.
• Is Part Of: Microelectronics journal. Volume 128(2022)
• Publication Date: 2022-10
• Subjects: Operational transconductance amplifier -- Miller compensation -- Multi-stage amplifier -- Settling time -- Q-reduction; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105538
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of p F which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor C m along with a feed-forward capacitor C f . The four-stage OTA uses only 500 fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510 ns under low quiescent power of 63 . 6 μ W for the wide range of load capacitors of 5 pF to 100 pF .