An efficient VLSI design of a new CRT-based reverse converter for the moduli set {2n, 22n − 1, 22n+1 − 1}. (26th March 2015) - Bankas, Edem Kwedzo; Gbolagade, Kazeem Alagbe
This paper presents an efficient reverse converter for a recently proposed 5n bit dynamic range moduli set {2 2n - 1, 2 n, 2 2n+1 - 1}. Our proposed converter is based on the New Chinese Remainder Theorem I scheme. The resulting architecture is adder based and memoryless consisting of two CSAs, three CPAs and a multiplexer which makes it suitable for efficient VLSI implementation. The proposed scheme is evaluated both theoretically and experimentally. From the theoretical point of view, our reverse converter outperforms the best known equivalent state-of-the-art in terms of both speed and area cost. Additionally, FPGA implementation results indicate that, on the average, our proposed reverse converter achieves about 16.03% reduction in hardware resources when compared with the existing state-of-the-art reverse converters. Also, in terms of conversion time, our proposed reverse converter is approximately 9.46% faster than the best known state-of-the-art.