A 0.8–3.2 GHz PLL with wide frequency division ratio range. (October 2022)

• Record Type: Journal Article
• Authors: Wu, Jin; Li, Jinwen; Wu, Xudong; Wan, Chenggong; Zheng, Lixia; Sun, Weifeng
• Is Part Of: Microelectronics journal. Volume 128(2022)
• Publication Date: 2022-10
• Subjects: Low-jitter PLL -- Current-mode circuits -- DAC -- CCO; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105579
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: An improved phase-locked loop (PLL) with a wide frequency division ratio range is presented. A digital to analog converter (DAC) is used to separate the proportional path and integral path, thus the dynamic performance of PLL can be flexibly adjusted by DAC and the current-controlled oscillator (CCO). As the resistor in the second-order PLL is replaced by an equivalent circuit, the implemented PLL is insensitive to the process, voltage, and temperature (PVT) variation. Decoupling the relationship between loop bandwidth ω b and division ratio N improves the overall performance over a wide dynamic output frequency range. The PLL was implemented in TSMC 22 nm CMOS process and the chip occupies an area of 0.04 mm 2 . The measured output frequency is ranged from 0.8 GHz to 3.6 GHz. The phase noise is −107.3dBc@1 MHz and the integrated RMS jitters at 1.92 GHz is 3.36ps. The total power consumption at 1.92 GHz is 4.2 mW.