Low-power bulk-driven time-domain comparator with high voltage-to-time gain for ADC applications. (October 2022)

• Record Type: Journal Article
• Authors: Sanati, Roohollah; Khatib, Farzan; Javadian Sarraf, Mohammad; Kardehi Moghaddam, Reihaneh
• Is Part Of: Microelectronics journal. Volume 128(2022)
• Publication Date: 2022-10
• Subjects: Delay element -- Time-domain comparator -- Subthreshold -- Bulk-driven; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105555
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper, presents an ultra-low power time-domain comparator at low supplied voltages. In the proposed comparator structure, a novel delay element (DE) has been designed to produce a significantly high voltage-to-time gain, resulting in a high accuracy of the proposed comparator, saving of occupied area, and avoiding the extra power dissipation. The main idea of this work is to use the bulk terminal of a transistor as one of the comparator's inputs in the subthreshold region. The post-layout simulation results in 180 nm TSMC technology with a supply voltage of 1 V, show that the proposed comparator consumes about 250 nW, and the comparator's resolution is less than 0.4mv for 2.5 MHz clock frequency. Also, the Monte-Carlo analysis of the proposed time-domain comparator shows, the largest value of offset voltage is 2.8 mV. Finally, a 10-bit 0.5 V 91 kS/s monotonic SAR-ADC was designed and simulated using the proposed comparator. The power consumption of the ADC is 152 nW. The FoM of 2fJ/conversion-step proves the effectuality of the proposed comparator.