A low-jitter leakage-free digitally calibrated phase locked loop. (December 2020) - kazeminia, Sarang; Soltani, Arefeh
Highlights: A new calibration method is proposed for phase adjustment in digitally-assisted PLLs. Common problems in CP-PLLs, like mismatch between up and down current sources, and also the leakage problems on CP capacitor are resolved. The systematic jitter due to the leakage current and the periodic discharge on charge pump's capacitors is eliminated. Charge pumps and the loop filters are the main area consuming elements inside the PLL loop which dominantly determine the chip area. Consider that vary large capacitances are required in loop filter to provide the proper loop stability. In the proposed structure, the CP is eliminated. Using ACC and DAC inside the closed loop structure provides digital representation of the control voltage which facilitates the ability of lock detection and other control on loop behavior. The proposed digitally-assisted technique translates the loop state to a 10-bit digital word which can be used to achieve further stability and jitter performances. Generating digital words in PLL loop, the loop gain can be dynamically controlled by multiplying/dividing the accumulation step by 2 N . Also, the digital calibration loop can process the digital words to find the best-fit point for phase adjustment. Abstract: A digital calibration scheme is proposed to reduce the systematic jitter due to the periodic current leakage in charge pump phase-locked loops. Frequency acquisition is performed through a feed-forward digitally assisted path. Then, the calibration loop digitally accomplishes the phase adjustment. Lock time is improved by applying the dynamic control on loop gain during the frequency acquisition. Using 32 overshoots/undershoots for calibration, peak-to-peak and root-mean-square jitter are reduced to 1.78pS and 0.57pS at 1.6 GHz operating frequency, when 1.8 V supply is subject to 80 mV random noise. Phase noise at 1 GHz reference frequency achieves to −117dBc/Hz and −120dBc/Hz, at 1MHz offset frequency, when the calibration is accomplished for N = 16 and N = 32, respectively. All the design is implemented in a 0.15 mm 2 area, and consumes 3.35 mW power at 1.8 V supply. Post-Layout simulation results are presented using the Berkeley short-channel insulated-gate field-effect transistor model, version3, in a 0.18 µm technology. Graphical abstract: Image, graphical abstract