In‐memory calculation with embedded arithmetic and logic units for deep neural network. Issue 17 (21st June 2022) - Yu, Shuiyue; Fu, Jie; Lin, Zhiting; Peng, Chunyu; Wu, Xiulong
Abstract: The computation of multiplication in memory is a promising approach to reduce latency and improve the energy efficiency of intelligence edge processors. However, the multiplication operation in the analog domain is associated with complex peripheral circuits and low accuracy. In this letter, an static random‐access memory (SRAM) array with embedded low area cost arithmetic and logic units is proposed, which realizes high‐speed and high‐precision multi‐bit multiplication. The calculation delay is as low as 164 ps. The maximum integral non‐linearity (INL) is only 0.340 least significant bit, which is 1/16 of that of analog domain multiplication.