A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer. (October 2021)

• Record Type: Journal Article
• Authors: Tang, Xiaoke; Zhao, Xu; Hu, Ang; Liu, Dongsheng; Jin, Zirui
• Is Part Of: Microelectronics journal. Volume 116(2021)
• Publication Date: 2021-10
• Subjects: Frequency synthesizer (FS) -- Phase lock loops (PLL) -- Injection locked -- Phase interpolator; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105158
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW.