Phase locked-loop with decaying DC transient removal for three-phase grids. (December 2022)

• Record Type: Journal Article
• Authors: Liu, Xiaokang; Xiong, Liansong; Wu, Binbing; Qian, Yang; Liu, Yonghui
• Is Part Of: International journal of electrical power & energy systems. Volume 143(2022)
• Publication Date: 2022-12
• Subjects: Decaying DC component -- Phase locked-loop -- Transient signal -- Unbalanced grid -- Harmonics; Electrical engineering -- Periodicals; Electric power systems -- Periodicals; Électrotechnique -- Périodiques; Réseaux électriques (Énergie) -- Périodiques; Electric power systems; Electrical engineering; Periodicals; 621.3
• DOI: 10.1016/j.ijepes.2022.108508
• Languages: English
• ISSNs: 0142-0615

Abstract

Abstract: Frequency and phase of the power grid, which are critical for reliable control and protection of grid-tied devices, are generally detected by the closed-loop phase locked-loop (PLL). In highly inductive high-voltage transmission systems, decaying DC (DDC) components with large amplitude can be easily introduced by load disturbances and/or grid abnormalities, leading to severe performance degradation of the PLL during the transient. Focusing on this issue, in this paper, modifications to the conventional synchronous reference frame (SRF)-PLL have been made to address the short-term disturbances including the DDC component, and the system operation is divided into the normal state and the DDC-transient state. The SRF-PLL is only adopted for the normal state where the DDC component is negligible. In the presence of a significant DDC component, as well as disturbances including negative-/zero-sequence components and harmonics, the weak effectiveness of the conventional SRF-PLL is proved, and an efficient DDC component extraction method, with a detection time of 0.5 grid cycle, is introduced for the three-phase system. The real-time amplitude and phase of the positive-sequence component can be efficiently extracted via the proposed scheme, by exploiting the transient signal properties in the dq -frame and assuming a constant grid frequency during the short transient. Finally, a proper design of switching logic has been proposed to allow for the fast and precise transition between the normal and the DDC-transient state, thereby ensuring high steady-state accuracy as well as short-term DDC transient immunity. Hardware-in-the-loop based experiments have been used to verify the effectiveness of the proposed PLL technique. Highlights: Decaying DC (DDC) components lower performance of traditional closed-loop phase locked-loop (PLL). Proposed PLL scheme efficiently detects grid phase in presence of DDC components. DDC transient criterion is designed based on positive-sequence signal and SNR. Proper measures increase phase detection speed/accuracy at transient start/end.