A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique. Issue 3 (29th July 2021)

• Record Type: Journal Article
• Authors: Sam, D.S. Shylu; Paul, P. Sam
• Is Part Of: Circuit world. Volume 47:Issue 3(2021)
• Page Start: 274
• Page End: 283
• Publication Date: 2021-07-29
• Subjects: Op-amp sharing technique -- Parallel sampling technique -- Pipelined ADC; Electronic circuits -- Design and construction -- Periodicals; Electronic circuits -- Periodicals; 621.381505
• DOI: 10.1108/CW-12-2020-0356
• Languages: English
• ISSNs: 0305-6120

Abstract

Abstract : Purpose: In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach: Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings: This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value: Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.