A 14 Gbps VCSEL driving ASIC in 55 nm for NICA multi purpose detector project. (1st August 2022)

• Record Type: Journal Article
• Authors: Zhao, C.; Chen, Q.; Guo, Z.; Arteche, R.; Ceballos, C.; Fang, N.; Gan, Y.; Murin, Y.; Yi, L.; Guo, D.; Sun, X.
• Is Part Of: Journal of instrumentation. Volume 17:Number 8(2022)
• Publication Date: 2022-08-01
• Subjects: Analogue electronic circuits -- Front-end electronics for detector readout -- Data acquisition circuits; Optical detector readout concepts; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/17/08/C08021
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. It consists of an equalizer stage, a limiting amplifier stage and an output driver stage. The equalizer stage uses the CTLE structure to compensate the high frequency losses at the PCB traces, bonding wires and input pads. To meet both the gain/bandwidth requirements and the area restriction, the limiting amplifier stage adopts the inductor-shared peaking technology. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed. This ASIC has been integrated with the VCSEL array in a customized optical module for the optical test. The test results show the wide-open 14 Gbps optical eye diagram with a measured RMS jitter of 2.7 ps and a peak-to-peak jitter of 17.4 ps, respectively.