Active DC‐link balancing and voltage regulation using a three‐level converter for split‐link four‐wire system. Issue 12 (1st September 2020)

• Record Type: Journal Article
• Authors: Manandhar, Ujjal; Zhang, Xinan; Gooi, Hoay Beng; Wang, Benfei; Fan, Feng
• Is Part Of: IET power electronics. Volume 13:Issue 12(2020)
• Page Start: 2424
• Page End: 2431
• Publication Date: 2020-09-01
• Subjects: distributed power generation -- capacitors -- invertors -- electromagnetic compatibility -- voltage control; split‐link four‐wire system -- four‐wire inverter -- three‐leg inverter topology -- split capacitor suffers -- poor DC link voltage regulation -- poor DC link voltage utilisation -- four‐leg inverter topology suffers -- split link inverter -- active balancing capability -- active balancing inverter -- constant DC link voltage -- converter topology -- controllable DC link voltage -- half DC link voltage; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2020.0067
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : The integration of the distributed generation to the unbalanced loads or the grid requires a three‐phase four‐wire inverter. The three‐phase four‐wire inverter could be of three‐leg or four‐leg topology. However, both the topologies have their drawbacks. The three‐leg inverter topology with a split capacitor suffers from poor DC link voltage regulation and poor DC link voltage utilisation. The four‐leg inverter topology suffers from poor electromagnetic compatibility. To solve these problems, the split link inverters with active balancing capabilities are studied by many researchers. The split link inverter with an active balancing inverter requires a constant DC link voltage and has less flexibility regarding the variation of the DC link voltage. In this study, a new converter topology is proposed, which provides the controllable DC link voltage to split link inverter with active balancing capability and also reduces the voltage stress to semiconductor switches to half DC link voltage. The detailed description of the proposed converter topology, design of the controller, and control hardware‐in‐the‐loop verification are presented in this study.