Degradation induced by hot carrier and cold carrier in 65‐nm NMOSFETs with enclosed gate and two‐edged gate layouts. (1st August 2018)

• Record Type: Journal Article
• Authors: Shen, Jingyu; Zhang, Ming; Li, Wei; Fan, Xue; Li, Jianjun; Tan, Can
• Is Part Of: Micro & nano letters. Volume 13:Number 8(2018)
• Page Start: 1096
• Page End: 1100
• Publication Date: 2018-08-01
• Subjects: CMOS integrated circuits -- hot carriers -- annealing -- semiconductor device reliability -- MOSFET circuits -- radiation hardening (electronics); constant voltage stress -- cold carrier contribution -- HCE damage -- enclosed gate NMOSFET -- two‐edged gate NMOSFET -- hot carrier reliability -- hot carrier stress -- complementary metal‐oxide‐semiconductor technology -- NMOSFET -- N‐channel metal‐oxide‐semiconductor field effect transistors -- enclosed gate layouts -- two‐edged gate layouts -- annealing bias -- CMOS technology -- total‐dose radiation tolerance -- CMOS circuits -- size 65.0 nm; Nanotechnology -- Periodicals; Nanostructures -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1049/mnl.2017.0850
• Languages: English
• ISSNs: 1750-0443

Abstract

Abstract : In this work, performance degradation of 65 nm N‐channel metal‐oxide‐semiconductor field effect transistors (NMOSFETs) with enclosed gate and two‐edged gate layouts under hot carrier stress and constant voltage stress is investigated. Compared with the cold carrier, the hot carrier effect (HCE) causes more serious degradation in threshold voltage and transconductance. It is shown that cold carrier contribution is reversible, while HCE damage is permanent, it cannot be reversed by application of the annealing bias. Meanwhile, an enclosed gate NMOSFET is proved to have higher resistance to HCE than two‐edged gate NMOSFET fabricated in the same 65 nm complementary metal‐oxide‐semiconductor (CMOS) technology according to the results of experiments. That is, the enclosed gate NMOSFET not only provides total‐dose radiation tolerance but also improves the hot carrier reliability of advanced CMOS circuits. The contributions of the two types of carriers to the degradation of transistor performance are analysed. The physical mechanism of HCE reliability of different geometry MOSFETs is studied.