High-speed pre-accumulator and post-multiplier for convolution neural networks with low power consumption. Issue 3 (3rd October 2022)

• Record Type: Journal Article
• Authors: Priyadarshini, K. Mariya; Ravindran, R.S. Ernest; Sujatha, M.; Kumar, K.T.P.S.
• Is Part Of: International journal of internet protocol technology. Volume 15:Issue 3/4(2022)
• Page Start: 139
• Page End: 147
• Publication Date: 2022-10-03
• Subjects: convolution neural networks -- Vedic sutras -- carry save adder -- flip-flop -- multiplier and accumulator; File Transfer Protocol (Computer network protocol) -- Periodicals; Multicasting (Computer networks) -- Periodicals; 004.678
• Languages: English
• ISSNs: 1743-8209

Abstract

In today's phase of growing technology Convolution Neural Networks (CNNs) are all over the places. It is a thriving segment in machine learning and Artificial Intelligences (AI) techniques. CNN needs bulk amount of computing competence and memory with higher frequency range. In this present investigation, Pre-Accumulator and Post-Multipliers (PAPM) are proposed which accelerate the speed of processor. 4-bit multiplier using Carry Save Adder (CSA) is built with 6Transistors-Adder and sutras of Vedic mathematics is constructed. Accumulator of multiplier and accumulator are designed with Two Level Edge Triggering Flip-Flops (TLET-FF) to increase bandwidth of the memory. The proposed architecture of Multiply Accumulate (MAC) circuit consumes very less power when compared to existing high speed MACs. Performance of accumulator is contrasted with three different, two-level triggered flip-flops namely 16TLET-FF, 14TLET-FF and 12TLET-FFs. The projected MAC replaces the existing multipliers due its low power together with high frequency of operation.