Comparing techniques for spur reduction in digital bang‐bang PLLs. Issue 8 (1st April 2013)

• Record Type: Journal Article
• Authors: Maffezzoni, P.; Marucci, G.; Levantino, S.; Samori, C.
• Is Part Of: Electronics letters. Volume 49:Issue 8(2013)
• Page Start: 527
• Page End: 529
• Publication Date: 2013-04-01
• Subjects: digital phase locked loops -- oscillators; digital bang‐bang PLL -- digital bang‐bang phase‐locked looper -- unwanted output spur tones -- high noise floor -- spur reduction technique -- dithering -- oscillator intrinsic noise -- loop design; digital phase locked loops -- oscillators; digital bang‐bang PLL -- digital bang‐bang phase‐locked looper -- unwanted output spur tones -- high noise floor -- spur reduction technique -- dithering -- oscillator intrinsic noise -- loop design; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.4402
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Bang‐bang phase‐locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor.