1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks. (11th June 2022) - Minguet Lopez, Joel; Rafhay, Quentin; Dampfhoffer, Manon; Reganaz, Lucas; Castellani, Niccolo; Meli, Valentina; Martin, Simon; Grenouillet, Laurent; Navarro, Gabriele; Magis, Thomas; Carabasse, Catherine; Hirtzlin, Tifenn; et al.
Abstract: Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio‐inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R (1 Selector 1 Resistor) device composed of a HfO2 ‐based OxRAM memory stacked on a Ge‐Se‐Sb‐N‐based ovonic threshold switch (OTS) back‐end selector is proposed for high‐density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field‐driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity. Abstract : 1S1R pertinence for binarized spiking neural network synaptic weight hardware implementation is demonstrated. Ovonic threshold switch selector switching dynamics are elucidated by crossing experimental data with novel Monte Carlo simulations. 1S1R reading conditions are optimized for low reading bit error rate during high‐frequency inference. Focusing on the MNIST recognition task, 1 MHz high‐frequency inference capabilities with 97% accuracy are demonstrated, with an estimated circuit area lower than 0.01 mm 2 .