A Fully Integrated System‐on‐Chip Design with Scalable Resistive Random‐Access Memory Tile Design for Analog in‐Memory Computing. (1st May 2022)

• Record Type: Journal Article
• Authors: Cai, Fuxi; Yen, She-Hwa; Uppala, Apurva; Thomas, Luke; Liu, Tianchi; Fu, Peter; Zhang, Xiaofeng; Low, Ambrose; Kamalanathan, Deepak; Hsu, Joe; Ayyagari-Sangamalli, Buvna
• Is Part Of: Advanced intelligent systems. Volume 4:Number 8(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-05-01
• Subjects: analog in-memory computing -- one-transistor-one-resistor -- resistive random-access memory; Artificial intelligence -- Periodicals; Robotics -- Periodicals; Control theory -- Periodicals; 006.3
• DOI: 10.1002/aisy.202200014
• Languages: English
• ISSNs: 2640-4567

Abstract

Abstract : As the demands of big data applications and deep learning continue to rise, the industry is increasingly looking to artificial intelligence (AI) accelerators. Analog in‐memory computing (AiMC) with emerging nonvolatile devices enable good hardware solutions, due to its high energy efficiency in accelerating the multiply‐and‐accumulation (MAC) operation. Herein, an Applied Materials custom‐designed system‐on‐chip (SoC) targeting AI applications with analog in‐memory computing using resistive random‐access memory (ReRAM) as the compute element is demonstrated. The first silicon achieves high energy efficiency in MAC operations. This chip is implemented with LeNet‐1 neural network on ReRAM tiles and demonstrated by Modified National Institute of Standards and Technology (MNIST) classification with accuracy matching that predicted in the simulations. A simulation framework, AI Sim, is also developed to evaluate the system performance for large‐scale application and guide the bitcell development and design choices. Abstract : Analog in‐memory computing with resistive random‐access memory (ReRAM) is promising due to its high speed and low power for multiply‐and‐accumulate (MAC) operations. Our system‐on‐chip (SoC) that fully integrates ReRAM tiles with essential analog peripheral circuitry and a RISCV processor is designed, which demonstrates high accuracy and energy efficiency in image classification and scalability for accelerating large‐scale neural networks.