A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM. (September 2022)

• Record Type: Journal Article
• Authors: Pandey, Sujata; Kumar, Saket; Bhatnagar, Vipul; Sharma, Richa; Baba basha, D.; Dhiman, Preeti
• Is Part Of: Computers & electrical engineering. Volume 102(2022)
• Publication Date: 2022-09
• Subjects: Current sense amplifier -- Reduced delay -- Leakage -- Low voltage SRAM; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2022.108216
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: A new current conveyor for static random access memory current sense amplifier is proposed for dual read bit-line cells. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The circuit exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size. Abstract: A new current conveyor for Static Random Access Memory current sense amplifier is proposed for dual read bit-line cells. The first stage of sense amplifier is current conveyor that turns to a latch with substrate bias assistance, also reduces leakage during no sense period. Regenerative action is improved for faster latching action and operation at lower supply voltages. Simulation is performed using TSMC 65 nm, BSIM level 54 and results compared with the earlier suggested current sensing schemes. The proposed circuit consumes average power of 6.54µW for typical capacitance of 100fF bit-line and data-line capacitance and maximum power of 8.07μ W at bit line capacitance as high as 200fF. Leakage current when sense amplifier is disabled, is only 80.4fA which is 2 × 10 −5 × the latch-type circuit. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The delay of proposed circuit is just 12% of the conventional latch type circuit. Higher sensitivity of the proposed circuit ensures small memory cell size while maintaining basic stability and reliability. The proposed circuit was simulated for various memory sizes and 1 GHz clock frequency and exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size when compared with the earlier suggested sensing schemes. Graphical abstract: Image, graphical abstract