Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network. (September 2022)

• Record Type: Journal Article
• Authors: A, Sasikumar; Ravi, Logesh; Kotecha, Ketan; V, Indragandhi; V, Subramaniyaswamy
• Is Part Of: Computers & electrical engineering. Volume 102(2022)
• Publication Date: 2022-09
• Subjects: Binarized neural network -- Deep learning -- Hardware accelerator -- Adaptive spatial amplitude -- FPGA; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2022.108302
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Adaptive spatial amplitude model is propose to reduce complexity of BNN accelerator. To explore the neural network structure to model the 1-bit BNN accelerator. A reconfigurable BNN accelerator on FPGA is implemented to increase the throughput. Demonstrate the performance of BNN accelerator with VGG-16 on various platforms. Abstract: Binarized neural networks (BNNs) architecture play a vital role in the development of deep learning accelerator for memory-constrained IoT devices. However, the cost-efficiency of the domain-specific accelerators still requires a simplified structure to enhance the computing performance of BNNs. We propose and present a reconfigurable BNN accelerator to improve the computing speed through channel amplitude and an adaptive spatial amplitude model. To reduce the redundant operations in the binarization of matrix multiplication, we introduce the channel amplitude model for BNN convolution functions. The adaptive spatial amplitude is implemented with the help of a matrix multiplication layer with 3 × 3 convolutions to get spatial information and increases the computation speed. For hardware implementation, the channel amplitude conversion is deployed through XNOR-popcount convolutions of each layer. The performance results of our proposed accelerator provide 2–10 × line buffer efficiency, 1.6–3.7 × processing frequency enhancement, and 2.35 × processing element reduction compared with existing baselines using VGG-16 based FPGA implementation. Graphical abstract: Image, graphical abstract