Sleepy Stack CSVCO with wide tuning and low power for PLL applications. Issue 1 (1st August 2022)

• Record Type: Journal Article
• Authors: Annamma, Kalaka; Saxena, Sobhit; Patel, Govind Singh
• Is Part Of: Journal of physics. Volume 2327:Issue 1(2022)
• Publication Date: 2022-08-01
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/2327/1/012013
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: This paper describes the implementation of low power leakage technique called Sleep-Stack in a Current Starved Voltage Controlled Oscillator (VCO) a block of Phase Locked Loop (PLL). The VCO is a electronic oscillator, whose oscillation frequency is decided by the control voltage. The major issue in the VCO is the power consumption, which has an impact on the performance of the PLL. The VCO that limits the current is preferred than the other oscillator which is called as Current Starved VCO. The work i.e. the design of Current Starved VCO is implemented using low power leakage technique called Sleepy Stack. This has been implemented in 45nm CMOS Technology with a supply voltage of 1.2 V in Cadence Software. The parameters like average power, oscillation frequency, and delay are calculated for this technique. The corner analysis has been performed for all this technique to verify the stable/linearity even in the worst case scenario. It has been observed that the sleepy stack technique with gain 23.99 GHz/V, phase noise -63.8dBc/Hz, Figure of Merit value of -142.234dBc/Hz and having frequency tuning range of 77.79%.The average power obtained for the Sleepy Stack technique is 11.88nW which is less than that of the existing CSVCO.