A low noise 5.12 GHz PLL ASIC in 55 nm for NICA multi purpose detector project. (1st September 2022) - Zhao, C.; Guo, D.; Chen, Q.; Guo, Z.; Arteche, R.; Ceballos, C.; Fang, N.; Gan, Y.; Murin, Y.; Yi, L.; Sun, X.; ,
Abstract: This paper presents the design and the test results of a low noise PLL ASIC for the optical data transmission system in NICA MPD project. In the proposed PLL, a novel charge pump circuit uses two feedback operational amplifiers to obtain low leakage current and reduce dynamic mismatch. A LC-VCO circuit combines the two-step capacitor tuning structure and the novel capacitor array unit to obtain a reasonable frequency range and an optimized Q factor performance. The PLL ASIC has been fabricated in a 55 nm CMOS process. The test results show that the PLL ASIC outputs the 5.12 GHz clock with a phase noise of −108 dBc/Hz at 1 MHz offset and a rms jitter of 880 fs. The PLL core consumes 22.2 mW from a 1.2 V power supply.