A CPU‐FPGA heterogeneous approach for biological sequence comparison using high‐level synthesis. (2nd October 2020)

• Record Type: Journal Article
• Authors: Jorge, Carlos A. C.; Nery, Alexandre S.; Melo, Alba C. M. A.; Goldman, Alfredo
• Other Names: Jeon Gwanggil guestEditor.; Abdellah Chehri guestEditor.; Cuomo Salvatore guestEditor.; Din Sadia guestEditor.; Jabbar Sohail guestEditor.; Kosta Sokol guestEditor.; Laccetti Giuliano guestEditor.; Lapegna Marco guestEditor.; Mele Valeria guestEditor.; Montella Raffaele guestEditor.
• Is Part Of: Concurrency and computation. Volume 33:Number 4(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-10-02
• Subjects: biological sequence comparison -- dynamic programming -- field‐programmable gate array -- high‐level synthesis -- longest common subsequence; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.6007
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: This article presents a high‐level synthesis implementation of the longest common subsequence (LCS) algorithm combined with a weighted‐based scheduler for comparing biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using Vivado High‐Level Synthesis tool, which is able to synthesize register transfer level (RTL) from high‐level language descriptions, such as C/C++. Performance and energy consumption results were obtained with a CPU Intel Core i7‐3770 CPU and an Alpha‐Data ADM‐PCIE‐KU3 board that has a Xilinx Kintex UltraScale XCKU060 FPGA chip. We executed a batch of 20 comparisons of sequences on 10k, 20k, and 50k sizes. Our experiments showed that the energy consumption on the combined approach was significantly lower when compared to the CPU, achieving 75% energy reduction on 50k comparisons. We also used the tool proposed in this article to do a case study on Covid‐19, with real SARS‐CoV‐2 sequences, comparing their LCS scores.