A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology. (26th January 2017)

• Record Type: Journal Article
• Authors: Zhang, Yi; Meng, Qiao; Zhang, Changchun; Zhang, Ying; Guo, Yufeng; Zhang, Youtao; Li, Xiaopeng; Yang, Lei
• Other Names: Gao Hao Academic Editor.
• Is Part Of: Journal of sensors. Volume 2017(2017)
• Publication Date: 2017-01-26
• Subjects: Detectors -- Periodicals; 681.205
• DOI: 10.1155/2017/3984526
• Languages: English
• ISSNs: 1687-725X

Abstract

Abstract : A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC's performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μ m × 930 μ m. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.