FinFETs: From Devices to Architectures. (7th September 2014)

• Record Type: Journal Article
• Authors: Bhattacharya, Debajit; Jha, Niraj K.
• Other Names: Abu Qahouq Jaber Academic Editor.
• Is Part Of: Advances in electronics. Volume 2014(2014)
• Publication Date: 2014-09-07
• Subjects: Electronics -- Periodicals; Electronics; Periodicals; 621.381
• DOI: 10.1155/2014/365689
• Languages: English
• ISSNs: 2356-6663

Abstract

Abstract : Since Moore's law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.