Asymmetrical multilevel converter topology with reduced number of components. Issue 6 (1st July 2013)

• Record Type: Journal Article
• Authors: Babaei, Ebrahim; Farhadi Kangarlu, Mohammad; Hosseinzadeh, Mohammad Ali
• Is Part Of: IET power electronics. Volume 6:Issue 6(2013)
• Page Start: 1188
• Page End: 1196
• Publication Date: 2013-07-01
• Subjects: cascade networks -- driver circuits -- invertors -- switching convertors; asymmetrical multilevel converter topology -- cascaded multilevel converter -- switching devices -- gate driver circuits -- design parameters -- cascaded basic units -- operational conditions -- dc voltage source value determination -- PSCAD/EMTDC simulation -- 51‐level inverter; cascade networks -- driver circuits -- invertors -- switching convertors; asymmetrical multilevel converter topology -- cascaded multilevel converter -- switching devices -- gate driver circuits -- design parameters -- cascaded basic units -- operational conditions -- dc voltage source value determination -- PSCAD/EMTDC simulation -- 51‐level inverter; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2012.0497
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : In this study, firstly a new basic unit is proposed for multilevel converters. The proposed basic units are used as building blocks to form a cascaded multilevel converter. In other words, the proposed topology consists of cascaded basic units. The proposed basic unit and the proposed multilevel converter use lower number of switching devices and gate driver circuits. In the proposed topology, two design parameters are available: the number of cascaded basic units and the number of dc voltage sources in each basic unit. These two parameters can be used to design the desired multilevel converter based on the operational conditions. Therefore the proposed topology offers good flexibility in designing. An algorithm for determining the values of the dc voltage sources is given in order to generate maximum number of voltage levels. The comparison results with some recently introduced topologies show that the proposed topology effectively reduces the components count. The simulation results obtained in PSCAD/EMTDC as well as the experimental results of a 51‐level inverter based on the proposed topology are presented to verify its performance.