Simplified hybrid space vector modulation for multilevel diode clamped converter. Issue 17 (28th January 2021)

• Record Type: Journal Article
• Authors: Bouzidi, Mansour; Barkat, Said; Krama, Abdelbasset
• Is Part Of: IET power electronics. Volume 13:Issue 17(2020)
• Page Start: 3861
• Page End: 3870
• Publication Date: 2021-01-28
• Subjects: support vector machines -- table lookup -- torque control -- field programmable gate arrays -- matrix algebra -- PWM power convertors -- Matlab; multilevel diode -- simplified hybrid space vector modulation algorithm -- space vector modulation algorithms -- abc coordinates -- αβ coordinates -- simplified SVM algorithm -- generalised SVM algorithm -- HSVM algorithm -- adjacent switching vectors -- triangles identification stage -- switching sequence definition -- DCC level -- computational processes -- reference voltage vector -- abc‐coordinates -- coordinates transformation -- minimum computational burden -- three‐level DCC laboratory prototype -- computational resources requirement; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2020.0529
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : This study proposes a new simplified hybrid space vector modulation (HSVM) algorithm for multilevel diode clamped converter (DCC). The main idea consists in combining the advantages of both space vector modulation (SVM) algorithms synthesised in abc and αβ coordinates to establish a new hybrid, simplified and generalised SVM algorithm. The HSVM algorithm offers a simple method to compute the duration time, automatic generation of all redundant states of the adjacent switching vectors without triangles identification stage and switching sequence definition for any DCC level. Moreover, all the computational processes are performed in one unique sector thanks to the proposed new reference voltage vector defined in abc ‐coordinates. The proposed algorithm does not require any coordinates transformation or lookup tables. Also, it can be implemented with minimum computational burden using a low resources digital platform. The proposed HSVM is verified through MATLAB simulation and validated experimentally using three‐level DCC laboratory prototype. For high‐level DDC, the HSVM is tested in real time using hardware‐in‐the loop testing technology. Different case studies are performed to demonstrate the high performance of the proposed HSVM and its ability in lowering the computational resources requirement.