SiC trench MOSFET with heterojunction diode for low switching loss and high short‐circuit capability. Issue 8 (11th June 2019)

• Record Type: Journal Article
• Authors: An, Junjie; Hu, Shengdong
• Is Part Of: IET power electronics. Volume 12:Issue 8(2019)
• Page Start: 1981
• Page End: 1985
• Publication Date: 2019-06-11
• Subjects: wide band gap semiconductors -- MOSFET -- silicon compounds -- semiconductor heterojunctions -- semiconductor diodes -- failure analysis -- semiconductor device reliability; gate oxide layer -- gate oxide corner -- switching losses -- short‐circuit capability -- low switching loss -- merged heterojunction diode -- parasitic body diode -- conventional silicon carbide trench MOSFET -- grounded P+ shield layer -- numerical analysis -- electric field concentration -- breakdown voltage -- Miller charge -- failure mechanism -- fabrication procedure -- SiC; Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/iet-pel.2019.0035
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract : A SiC trench MOSFET with a merged heterojunction diode is proposed and numerically analysed here. The merged heterojunction diode can effectively suppress the turn‐on of the parasitic body diode in the proposed SiC trench MOSFET. In addition, a P + shield layer surrounding the gate oxide layer can dramatically alleviate the gate oxide corner from the concentration of the electric field and improve the static and dynamic performances of the proposed device. As a result, not only the breakdown voltage is increased by 24% but also the miller charge and the switching losses of the proposed structure are reduced by 43 and 48.6%, respectively, when compared with those of the conventional SiC trench MOSFET with a grounded P + shield layer. Moreover, the short‐circuit capability and its failure mechanism are numerically studied for the proposed structure. Finally, a feasible fabrication procedure is provided to realise the fabrication of this new device.