Analysis and design of a new fault‐tolerant digital comparator based on nano‐scale quantum technology. (31st July 2022)

• Record Type: Journal Article
• Authors: Jiao, Yuhan
• Other Names: Wright Steven A. guestEditor.; Solak Serdar guestEditor.; Kilimci Zeynep Hilal guestEditor.; Eken Süleyman guestEditor.; Fernandes Steven guestEditor.; Zhang Yu‐Dong guestEditor.; Tavares João Manuel R.S. guestEditor.
• Is Part Of: Concurrency and computation. Volume 34:Number 20(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-07-31
• Subjects: comparator -- fault‐tolerant -- nano -- QCA technology; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.7158
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Quantum‐dot cellular automata (QCA) is a transistor‐free technique for designing digital circuits. It is a substitute for CMOS technology for producing low‐energy and high‐speed digital circuits. In addition, the digital comparator is an important digital circuit; its fault‐tolerant design is examined in this article. Additionally, a coplanar QCA‐based fault‐tolerant comparator circuit with a small number of cells is suggested. The QCADesigner is used to achieve exact simulation results. The suggested fault‐tolerant comparator requires 63 QCA cells, uses 0.8 μ $$ \upmu $$ m 2, and has three clock cycles delay in accomplishing its purpose. Furthermore, simulation results demonstrate that the suggested comparator design with a limited number of cells can achieve a fault‐tolerant of 80% against cell missing, extra cell, cell displacement, and cell rotation faults.