Improvement of Phase‐Change Memory Performance by Means of GeTe/Sb2Te3 Superlattices. Issue 3 (1st March 2021) - Térébénec, Damien; Castellani, Niccolo; Bernier, Nicolas; Sever, Vitomir; Kowalczyk, Philippe; Bernard, Mathieu; Cyrille, Marie-Claire; Tran, Nguyet-Phuong; Hippert, Françoise; Noé, Pierre
Abstract : GeTe/Sb2 Te3 superlattices (SLs) obtained by sputtering are integrated in phase‐change memory (PCM) devices with a "wall structure". The high structural quality of SLs deposited on TiN or SiN x layers, used as metallic bottom heater and dielectric bottom layer in PCM devices, is established by X‐ray diffraction, for as‐grown SLs and after an annealing corresponding to the maximum thermal budget during the integration process. Scanning transmission electron microscopy (STEM) images of SLs within PCM cells confirm that the SL structure is kept after integration. A robust statistical analysis on a large number of devices demonstrates unambiguously that the RESET current is lower in SL devices than in GeTe reference devices and decreases when the Sb2 Te3 layer thickness in the SL increases from 2 to 8 nm. STEM imaging of a PCM cell incorporating an SL demonstrates that switching from the low‐ to the high‐resistance state occurs through a melting–quenching process and is not due to crystal–crystal transition or defect reorganization in the SL, in contrast to what is commonly stated in the literature on interfacial phase‐change memories (iPCMs). The origin of the improved switching performance of SL‐based PCM devices is discussed, linked with the impact of swapped bilayers. Abstract : GeTe/Sb2 Te3 superlattices are successfully integrated in phase‐change memory (PCM) devices. Superlattice devices require lower RESET current than standard PCM ones. Electron microscopy imaging of a superlattice device evidences its amorphization in the RESET state. A novel explanation of the origin of the decrease in the RESET current in superlattice devices when increasing the thickness of Sb2 Te3 layers is proposed.