An SEU fault injection platform for radiation-harden design debugging in the FPGA. (1st August 2022)

• Record Type: Journal Article
• Authors: Zhang, F.; Zhou, Z.; Wang, Y.; Wang, D.; Wu, M.; Zhu, L.
• Is Part Of: Journal of instrumentation. Volume 17:Number 8(2022)
• Publication Date: 2022-08-01
• Subjects: Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases) -- Radiation-hard electronics; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/17/08/P08007
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: An SEU fault injection platform was designed to ease the debugging of radiation-harden design in FPGA. The platform includes the FPGA being tested, the functional firmware being debugged, the essential-bit extraction algorithm based on Python, and the random fault injection algorithm. The platform can inject single-bit SEU failures, adjacent two-bit SEU failures, and three-bit SEU failures. It works in two modes: normal injection mode and essential-bit injection mode. Functional failure rate is the performance metric which used to evaluate the development. It is the probability of triggering a DUT function failure. In this experiment, the SEU fault injection platform is verified by measuring whether TCP/IP communication links are disconnected due to SEU faults. Experimental results show that the probability of TCP/IP link disconnection in normal injection mode is 0.13%, 0.23% and 0.25% respectively when random injection of single-bit SEU failure, adjacent two-bit SEU failure and multi-bit SEU failure occurs 10, 000 times. In the essential-bit injection mode, the probability of TCP/IP link disconnection caused by single-bit SEUs failure, adjacent two-bit SEUs failure and three-bit SEUs failure is 0.87%, 6.97% and 11.76% respectively, indicating a significant increase in the functional failure rates. This shows that the essential-bit injection mode can be used to expose problems more quickly and accelerate the debugging process of FPGA radiation-harden design.