A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application. (29th March 2018)

• Record Type: Journal Article
• Authors: Singar, Sumitra; Joshi, N. K.; Ghosh, P. K.
• Other Names: Rossi Marco Academic Editor.
• Is Part Of: Journal of nanotechnology. Volume 2018(2018)
• Publication Date: 2018-03-29
• Subjects: Nanotechnology -- Periodicals; Nanotechnology; Nanotechnology; Periodicals; Periodicals; 620.5
• DOI: 10.1155/2018/2934268
• Languages: English
• ISSNs: 1687-9503

Abstract

Abstract : Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.