Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor. Issue 2 (15th July 2020)

• Record Type: Journal Article
• Authors: Mewada, Hiren K.; Chaudhari, Jitendra; Patel, Amit V.; Mahant, Keyur; Vala, Alpesh
• Is Part Of: Circuit world. Volume 47:Issue 2(2021)
• Page Start: 184
• Page End: 193
• Publication Date: 2020-07-15
• Subjects: FPGA -- Synthetic aperture radar -- Chirp-scaling algorithm; Electronic circuits -- Design and construction -- Periodicals; Electronic circuits -- Periodicals; 621.381505
• DOI: 10.1108/CW-02-2020-0031
• Languages: English
• ISSNs: 0305-6120

Abstract

Abstract : Purpose: Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor. Design/methodology/approach: A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library. Findings: The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization. Originality/value: Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.