A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods. (19th September 2016)

• Record Type: Journal Article
• Authors: Ghaderi, Noushin; Erfani-jazi, Hamid Reza; Mohseni-Mirabadi, Mehdi
• Other Names: Deen M. Jamal Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2016(2016)
• Publication Date: 2016-09-19
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2016/8202581
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a 0.18 μ m CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.