Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate. (22nd September 2014)

• Record Type: Journal Article
• Authors: Singh, Gagandeep; Goel, Chakshu
• Other Names: Sang Liwen Academic Editor.
• Is Part Of: Advances in electronics. Volume 2014(2014)
• Publication Date: 2014-09-22
• Subjects: Electronics -- Periodicals; Electronics; Periodicals; 621.381
• DOI: 10.1155/2014/564613
• Languages: English
• ISSNs: 2356-6663

Abstract

Abstract : In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.