A 12‐bit SC3 partially segmented current steering DAC with improved SFDR and bandwidth. (4th May 2022) - Kumar, Abhishek; Gupta, Santosh Kumar; Bhadauria, Vijaya
Abstract: A 12‐bit self cascode capacitor compensated (SC 3 ) partial segmented current steering digital to analog converter (DAC) is proposed and implemented in standard 180‐nm CMOS technology. The effect of the output capacitance at a higher frequency of operation is analyzed. Based on the analysis, a self cascode transistor is connected on the top of the differential switch with an "always‐on" biasing without compromising the voltage headroom. Besides, a compensation capacitor is also used at the output to improve spur free dynamic range (SFDR), which is obtained as 108 dB when sampled at 800 MS/s. The proposed architecture also offers high output impedance by more than 10 times compared with the cascode device. The proposed design also enhances the bandwidth of the circuit and is obtained to be 4 GHz with a power supply rejection ratio (PSRR) of 43 dB. It also has a total harmonic distortion (THD) of <3% up to input power of −4 dB and is also insensitive to process variations with a sensitivity of <0.5%. Abstract : A 12‐bit self cascode capacitor compensated (SC 3 ) partial segmented process insensitive current steering digital to analog converter (DAC) is proposed and implemented in standard 180‐nm CMOS technology. The architecture improves dynamic performances, SFDR and bandwidth to 108 dB and 4 GHz, respectively. It also has a THD of <3% up to input power of −4 dB and a PSRR of 43 dB.