A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. (3rd May 2022) - Sahani, Jagdeep Kaur; Singh, Anil; Agarwal, Alpana
Abstract: A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz. Abstract : In this paper, a low jitter, low power, and fast locking dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is designed. A fast locking and lower power consumption in ADPLL is achieved with help of 3‐bit flash TDC. The novel low phase noise VCO is used to fasten the locking process, jitter reduction, and PVT variations. Proposed ADPLL achieves a jitter of 1.83 ps and locking time of 1.7 μs at frequency of 1.6 GHz.