A new high‐level boost inverter topology with reduced device count. (30th March 2022)

• Record Type: Journal Article
• Authors: Siddique, Marif Daula; Reddy, B.Prathap; Meraj, Mohammad; Iqbal, Atif
• Is Part Of: International journal of circuit theory and applications. Volume 50:Number 8(2022)
• Page Start: 2777
• Page End: 2792
• Publication Date: 2022-03-30
• Subjects: high‐level topology -- multilevel inverter -- single‐stage power conversion; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3280
• Languages: English
• ISSNs: 0098-9886

Abstract

Abstract: The requirement of a boosting aspect for the power electronic converter is essential for the fuel cell, solar PV, and battery‐based applications as the generated voltage is of low voltage magnitude. In these low‐voltage applications, a new boost inverter topology has been suggested, where the power conversion will happen in a single‐stage instead of two‐stage (dc–dc converter + two‐level inverter). The proposed topology consists of 11 power semiconductor devices, one switched capacitor unit, and two dc voltage sources that are arranged in the magnitude of 1:3. This arrangement is able to achieve an output voltage of 15 levels with a boosting factor of 1.75. The other advantages of the designed topology have been the reduced device count with the self‐balancing of capacitor voltage and improved efficiency with better power loss sharing among the switches. By accumulating additional switched‐capacitor units to the proposed basic structure, the proposed inverter can be extended to support a greater number of levels and a higher voltage gain. A comprehensive assessment has been accomplished with single‐source and dual‐source topologies, and the proposed topology shows the improved design. A low‐power laboratory porotype has been used to endorse the proposed topology with real‐time conditions. Abstract : The requirement of a boosting aspect for the power electronic converter is essential, and in this paper, a new boost inverter topology has been proposed. The proposed topology consists of 11 power semiconductor devices, one switched‐capacitor unit, and two dc voltage sources that are arranged in the magnitude of 1:3, to achieve an output voltage of 15 levels with a boosting factor of 1.75. A low‐power laboratory porotype has been used to endorse the proposed topology with real‐time conditions.